There is a general need for materials with low dielectric constants (low-k) in the integrated circuit manufacturing industry. Using low-k materials as the interlayer dielectric of conductive interconnects reduces the delay in signal propagation and signal crosstalk due to capacitive effects. The lower the dielectric constant of the dielectric, the lower the capacitance of the dielectric and the RC delay in the lines and signal crosstalk between electrical lines of the IC. Further, the use of low k materials as interlayer dielectric will reduce power consumption of complex integrated circuits.
Low-k dielectrics are conventionally defined as those materials that have a dielectric constant (k) lower than that of silicon dioxide (SiO2), that is k<˜4. Generally, they have a dielectric constant of 3 or less. Typical methods of obtaining low-k materials include introducing pores into the dielectric matrix and/or doping silicon dioxide with various hydrocarbons or fluorine. In technology nodes of 90 nanometers and beyond, carbon doped oxide dielectric materials look extremely promising. However, wide spread deployment of these materials in modern integrated circuit fabrication processes presents some technological hurdles.
Specifically, in comparison with silicon dioxide, low k CDO materials typically have inferior mechanical properties due to the incorporation of ending methyl groups (—CH3) in order to lower the k value of CDO materials. These mechanical properties include hardness, modulus, film residual stress, blanket film cracking threshold or limit, fracture toughness, etc. These properties are derived primarily from the strength of the atomic bonds and their binding energy. For instance, using conventional Si containing organics as precursors in a conventional plasma enhanced chemical vapor deposition (PECVD) process, the resulting dielectric CDO film will possess a dielectric constant of 2.7-2.95 with a hardness of 1.2-2.0 GPa, modulus of 6.6 to 12 GPa, and a blanket film cracking limit between 2.3-2.7 μm. It is noted that the cracking limit is an overall measure of mechanical properties of a CDO film. Many applications will require cracking thresholds of greater than 3 μm, and more preferably greater than 5 μm. CDO materials of inferior mechanical properties will have adhesive (delamination) and cohesive (cracking) failures during the Cu-low k integration and packaging steps. These failures are exacerbated by the increasing complexity of integrated circuits and manifest as growing numbers of metallization layers. It is not uncommon for a modern IC design to require nine metallization layers, each with a separate dielectric layer. Each of these dielectric layers will have to withstand mechanical stresses from, for example, Chemical Mechanical Polishing (CMP) and/or thermal and mechanical stresses incurred during IC packaging operations.
In addition to modulus, a mechanical property of growing importance is the residual (or internal) stress in a dielectric film. As explained below, residual stress is comprised of an extrinsic stress component and an intrinsic stress component. Further, residual stress can be either compressive or tensile. Conventional low k films (k<3.2), including CDO films, typically have a tensile stress in excess of 50 MPa. The residual stresses within a deposited dielectric film are of particular interest for this invention. In IC fabrication contexts, these stresses can manifest in different ways, including cracking initiation and propagation and bowing or arching of die, which indicate net tensile or compressive stress. Low residual stress leads to low cracking driving force, a high cracking or buckling limit and hence a low failure rate during Cu-low k integration and packaging.
FIG. 1a illustrates a dielectric film 105 deposited in a silicon substrate 110, in this case a carbon doped oxide (CDO) film (also known as an organo-silicate glass (OSG) film), where intrinsic tensile stress pulls the film in toward the center of the film and causes it to bend the substrate so that it is concave. A film of excessive tensile stress, such as a conventional CDO film, tends to initiate cracking spontaneously or under external influence. Further, the tensile stress tends to propel the crack propagation in the film. FIG. 1b is an illustration of a similar structure in which compressive stress pushes the film out (along the plane of the film) and causes it to bend the substrate so that it is convex. A film of excessive compressive stress tends to lead to film buckling or spontaneous delamination from the substrate. Thus a low residual stress, either tensile or compressive, of CDO film is important in the application in the Cu-low k integration and packaging.
FIG. 2 is a graph of wafer-level stress as a function of number of process steps for 90 nm CDO technology and 130 nm fluorinated silica glass (SiOF) technology. This figure was taken from Jan, C. H., et al, 90 NM Generation, 300 mm Wafer Low k ILD/Cu Interconnect Technology, 2003 IEEE Interconnect Technology Conference, which is incorporated herein by reference. As shown, each additional layer of CDO dielectric material increases the total tensile residual stress in the test wafer. Clearly, more process steps lead to larger tensile stresses in the film. In a typical IC device requiring 5 or more CDO layers, the tensile residual stress creates serious problems. Note in FIG. 2 that the tensile stress development in CDO stacks is partially offset by the compressive stress of a silicon oxide layer at the top. Even if such silicon oxide layer is used in a fabrication process, it cannot overcome the difficulties associated with significant tensile stress occurring at intermediate stages of the fabrication process.
Many device failures can ultimately be traced to stresses and their variations at various stages of IC processing. Those failures including interfacial delamination between different materials and cracking within one material during chemical mechanical polishing (CMP) and packaging. Excessive stress of thin films, such as CDO films, will also accumulate through multiple layer integration and will result in wafer warping and CMP issues. Since device feature size is continuously shrinking, stress related problems are expected to become more severe. Thus there is a high demand based on the current Cu-low k integration scheme that the stress of CDO films be lowered from the current level (˜50 MPa or greater tensile) while raising hardness/modulus and still retaining a low dielectric constant.